1. Field of the Invention
This invention relates to multi-threaded processors and, more specifically, to balancing instruction loads between multiple execution units within a multi-threaded processor.
2. Description of the Related Art
Modern computer processors typically include cores with multiple instruction execution units. Processor performance may be improved when multiple execution units process instructions in parallel. Some execution units are configured to process specific instruction types. For example, some execution units are configured to process integer-type instructions while other execution units are configured to process load/store instructions and still others are configured to process floating point or graphics instructions.
If the instruction load is not equally balanced between such execution units, processor performance may be slowed by instructions waiting for a particular execution unit to become available while other execution units sit idle or under-loaded.